1. Field of the Invention
This invention is related to integrated circuit memories and, more particularly, to memories which include redundant columns and/or rows for repairing defects.
2. Description of the Related Art
Various integrated circuits may include large memories in addition to logic circuits. The memories may include various random access memory (RAM) arrays (e.g. static RAM (SRAM) or dynamic RAM (DRAM) arrays). For example, system-on-a-chip (SOC) integrated circuits may include a variety of caches and other large memories used by the processors and other system components included on the chip. In many cases, the memories may comprise ½ or more of the integrated circuit (or chip) area.
The transistors forming the memory arrays are often packed more densely into the chip area occupied by the memory arrays, as compared to the transistors outside of the memory arrays (e.g. the transistors in the logic circuits). Accordingly, the memory arrays are more susceptible to manufacturing defects. In order to reduce the impact of manufacturing defects in the memory arrays on the yield of the integrated circuits, the memories often include redundant rows and/or columns that may be used to repair defective rows and columns in the memory array.
Generally, the memory array must be tested to determine if there are any defects in the memory array and then redundant rows and columns may be selected to replace rows and columns in the array to eliminate the defects. For example, once the defects are located, one may exhaustively attempt combinations of row and/or column replacements to find a solution that repairs the defects. Typically, the memory array testing is performed during the overall integrated circuit testing performed on each manufactured integrated circuit (e.g. using automatic test equipment (ATE)). Testing time on the ATE is generally expensive, and thus the exhaustive method may be too costly to implement.